When an AI application needs to reason, call tools, and respond to many people at the same time, counting FLOPS is not enough: the latency to generate each token, memory, and communication between accelerators end up defining the experience. The video below presents the Cerebras CS-4, a rack system based on silicon-wafer-sized processors. The proposal is ambitious, but the numbers need to be read for what they are: results and comparisons published by the manufacturer for specific scenarios.
Video summary: The Evolving AI channel explains the WSE-3 Turbo, the CS-4 rack, the Nexus platform, and why Cerebras is betting on low-latency inference instead of just grouping more GPUs.
Channel video Evolving AI: Cerebras’s New 900,000-Core AI Beast Chip That Made NVIDIA AI Servers Look Like a JOKE!.
CS-4: one rack, three wafers
The CS-4 is not a PCIe card to be installed in a standard server. It is a rack solution that brings together three Wafer-Scale Engine 3 Turbo (WSE-3T) processors. In the August 18, 2026 announcement, Cerebras states up to 750 PFLOPS from computing to AI, 129.6 PB/s of memory bandwidth and 7.2 Tb/s I/O per CS-4 system. These are datacenter infrastructure specifications, not a home lab alternative.
The central point of the architecture is to reduce the cost of coordinating many small units. A large model is typically split across accelerators; at each step, data and states need to cross memory, boards, and the network. Cerebras concentrates much more computation onto a single wafer and then brings the wafers closer together in the same rack design. To compare accelerator families and their tradeoffs, see also GPU vs. TPU: How AI Chips Work and How graphics cards work.
WSE-3 Turbo: why use the entire blade?
In conventional manufacturing, a silicon wafer is cut into several this. The Wafer-Scale Engine family follows a different route: it turns almost the entire wafer into a single processor. According to Cerebras, the WSE-3 Turbo occupies 46.225 mm², integrates 4 trillion transistors, 900 million AI-optimized cores and 44 GB of SRAM on the wafer itself. The Turbo version reaches 250 PFLOPS and 43.2 PB/s of memory bandwidth per wafer.
A large die inevitably contains manufacturing defects. Cerebras's approach is to design core and routing redundancy: defective regions can be disabled and bypassed. This doesn't make the silicon magically perfect; it is an architectural, testing, and software decision so that a flawed wafer can still become a product.
Nexus, Wafer-Scale Backpack and direct links
The CS-4 inaugurates the rack platform Nexus, separated into computing, power, and I/O modules. Each Wafer-Scale Backpack combines a wafer, power conversion, direct liquid cooling, high-speed I/O, and control electronics. By decoupling these modules, the company aims to simplify rack production, maintenance, and upgrades.
For the network, the system combines RoCE v2 over Ethernet with Direct Wafer Links. The first facilitates integration with Ethernet infrastructure; the second connects wafers within or between racks without a switch in the direct path. The company declares wafer-to-wafer latency of up to 2 microseconds. In distributed models, this type of latency can be as important as raw power, because each token generation requires state synchronization.
Prefill and decode: where speed appears
LLM inference is not a single stage. In the prefill, the system processes the entire prompt and builds the initial state; in the decode, it generates tokens one by one. Cerebras' proposed strategy is disaggregated inference: a GPU or ASIC can perform the prefill and the CS-4 can handle low-latency decode. The state between stages still needs to be transported efficiently, which is why interconnect and I/O are part of the proposal, not just accessories.
This helps explain the interest in agentic applications. An agent can switch between generation, tool calling, result reading, and new generation multiple times. Faster tokens reduce the wait time for each cycle, but they don't on their own solve for tool quality, security, testing, or observability. The heterogeneous architecture also appears in initiatives like the AWS Project Rainier.
up to 30x faster“
Cerebras disclosed more than 4.400 tokens per second per user in GPT-OSS-120B, under identical prompts, and an advantage of up to 30× over GPU solutions. The announcement footnote is essential: actual throughput varies with model architecture, context length, precision, and service configuration. Moreover, “GPU” is not a single comparable configuration.
Therefore, it is not correct to conclude that any AI workload will be 30× faster. The useful takeaway is that, for interactive decode in large models, processor-adjacent SRAM, bandwidth, and low latency between accelerators can meaningfully change the result. Independent benchmarks, price, availability, power consumption, and performance on different models remain necessary before a purchasing decision.
2015–2026: the history of Cerebras
The company's own timeline places its founding in 2015. Andrew Feldman, Gary Lauterbach, Michael James, Sean Lie, and Jean-Philippe Fricker created Cerebras to make wafer-scale computing viable in datacenters — an idea that seemed difficult to produce economically because larger chips suffer more from defects.
- 2019: the WSE-1 and the CS-1 system arrive.
- 2021: WSE-2 and CS-2 enter the scene; the company also highlights NETL research results with the system.
- 2022: Argonne National Laboratory researchers receive the Gordon Bell Special Prize for work on COVID-19 variants with a CS-2 cluster.
- 2023: Cerebras and G42 announce the Condor Galaxy supercomputer network; the CG-1 was disclosed with 4 exaFLOPS FP16 and 54 million cores.
- 2024: the WSE-3/CS-3 generation arrives on the market.
- 2025: the company expands its inference offering and cloud integrations; its timeline cites partners like Meta, Perplexity, Mistral, Hugging Face and OpenRouter.
- 2026: the corporate page reports trading on the Nasdaq under the ticker CBRS in May and the launch of CS-4 in August.
Who invested in Cerebras
Funding and commercial partnership are not the same thing. To avoid mixing the two, it's worth separating the investors named by the company in recent rounds from the strategic agreements.
- Series G (September 2025): US$ 1,1 billion round, with a post-money valuation of US$ 8,1 billion. It was led by Fidelity Management & Research Company and Atreides Management; participated Tiger Global, Valor Equity Partners and 1789 Capital, besides existing investors Altimeter, Alpha Wave Global and Benchmark.
- Series H (February 2026): US$ 1 billion round, with an approximate post-money valuation of US$ 23 billion. The leadership was by Tiger Global; the company cites Benchmark, Fidelity Management & Research Company, Atreides Management, Alpha Wave Global, Altimeter, AMD, Coatue and 1789 Capital, among other participants.
- G42: is primarily a strategic partner for Cerebras on the Condor Galaxy network. In the S-1 filing from 2024, the company also described an agreement for an affiliate of G42 to purchase US$ 335 million in preferred shares, subject to conditions and regulatory approvals. This agreement should not be automatically conflated with the investor lists from Series G and H.
This track record shows why Cerebras is more than an isolated chip: there is capital to manufacture hardware, operate datacenters, and compete in the inference market. At the same time, customer concentration, datacenter execution, energy, supply, and competition with GPU platforms and other ASICs remain material risks — points the company itself outlines in its investor disclosures.
What changes for those who use Linux and AI
The Linux user is unlikely to install a CS-4 at home. The practical effect will likely come through APIs and services: faster responses, lower-latency code generation, and agents that complete more steps within the same timeframe. For local use, the path remains accessible software and hardware, such as running local AI with Ollama on Linux.
Cerebras represents a significant bet: redesigning the accelerator, rack, and interconnect simultaneously. The video is useful for visualizing this architecture; however, the technical decision must be based on reproducible measurements, total cost of ownership, availability, and your workload's compatibility.
Primary sources: Cerebras timeline and founders · WSE-3 Turbo · CS-4 announcement and specifications · Nexus architecture and disaggregated inference · G Series · H Series · S-1 entry on G42.